1. Field of the Invention
The present invention relates, in general, to memory management for integrated circuits and systems, and more particularly, to management of shared memory resources which are accessible independently and asynchronously by multiple processes in an adaptive computing integrated circuit architecture.
2. Description of the Related Art
The related application discloses a new form or type of integrated circuit, referred to as an adaptive computing engine (“ACE”), which is readily reconfigurable, in real time, and is capable of having corresponding, multiple modes of operation.
The ACE architecture for adaptive or reconfigurable computing, includes a plurality of different or heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real time to adapt (configure and reconfigure) the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.
The ACE architecture utilizes a data flow model for processing. More particularly, input operand data will be processed to produce output data (without other intervention such as interrupt signals, instruction fetching, etc.), whenever the input data is available and an output port (register or buffer) is available for any resulting output data. Controlling the data flow processing to implement an algorithm, however, presents unusual difficulties, including for controlling data flow in the communication and control algorithms used in wideband CDMA (“WCDMA”) and cdma2000.
One aspect of data flow control is memory management, where a given memory, such as a First In-First Out (“FIFO”) memory, is shared by or across multiple processes. In such a shared arrangement, each process may access the memory, such as to read or write data. In the prior art, however, to avoid conflict in memory usage by these various processes, a “mutual exclusion” is implemented, either in hardware or software. With such a mutual exclusion, when one process is utilizing the shared memory, all other processes are excluded or “locked out” from accessing the shared memory.
Such mutual exclusion memory management, however, typically requires additional steps, additional instructions, or additional circuitry for a process to access the shared memory. As a consequence, such prior art memory management results in slower memory access, which is unsuitable for high speed operations.